LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier

Keywords: Low-power Adiabatic logic Energy recovery Multiplier a b s t r a c t As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development—of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity are common approaches used in conventional CMOS. In adiabatic switching circuits, the current flow through transistors can be significantly reduced by ensuring uniform charge transfer over the entire available time. This paper presents the simulation of this current in two-phase clocked adiabatic static CMOS logic (2PASCL) and conventional CMOS. From the SPICE simulations, at transition frequencies from 1 to 12 MHz, a 4 Â 4-bit array 2PASCL multiplier shows a maximum reduction in power dissipation of 77% relative to that of a static CMOS. The measurement results of a 4 Â 4-bit array 2PASCL multiplier demonstrate a 57% reduction compared to a 4 Â 4-bit array two-phase clocked adiabatic dynamic CMOS logic (2PADCL). These results indicate that 2PASCL technology can be advantageous when applied to low-power digital devices operated at low frequencies, such as radio-frequency identification (RFID) tags, smart cards, and sensors. Recently, power consumption has been a fundamental constraint in both high-performance and portable, energy-limited systems. In conventional CMOS circuits, power dissipation primarily occurs during device switching. A sudden flow of current through channel resistive elements results in half of the supplied energy being dissipated at each transition. In CMOS technology, as E diss ¼ 1 2 C L V 2 dd , circuit designers are focusing on how to reduce V dd and C L. However, power dissipation can also be reduced by reducing the current flow into the transistors. Low-power circuit systems achieved by implementing the concept of adiabatic switching [1] and energy recovery have been widely applied, and various energy-recovery circuits with adia-batic circuitry for ultra-low power implementation have been presented [1–12]. The essential idea of adiabatic charging is to design a circuit that allows all the nodes to be charged or discharged at a constant current. Power dissipation is minimized by decreasing the peak current flow through transistors. This flow is accomplished by using ramp-like power/clock signals [2]. The system draws some of the energy that is stored in the capacitors during a given computation step and uses this energy in subsequent computations. However, for a single …